Communications systems generally require that the operation of synchronous transmission elements within the system be coordinated to some timing signal derived from a reference clock signal. The derived timing signal is synchronized, or locked, to the reference clock signal. One well-known clock synchronization technique is the use of a phase locked loop (PLL).
A PLL is a frequency-selective circuit generally containing a phase comparator, a low-pass filter, and a voltage-controlled oscillator (VCO) coupled in a feedback arrangement. When an input or reference clock signal is applied to the PLL, the phase comparator compares the phase of the reference clock signal with the phase of the VCO output signal and generates an error signal that is related to the phase relationship between the two signals. This error signal is filtered, amplified, and applied to the VCO, thus driving the frequency of the VCO output signal in a direction to more closely align its phase to that of the reference clock signal. When the VCO output frequency is sufficiently close to the reference frequency, the feedback nature of the PLL causes the VCO output to lock to the reference clock signal frequency, with the exception of some finite phase difference. The point is called “zero phase error.” While the phases may not be aligned, their frequencies are matched such that the amount of phase difference remains substantially constant. The self-correcting nature of the PLL thus allows the system to track the frequency changes of the reference clock signal once it is locked. A frequency divider is often inserted in the feedback loop when the desired output frequency of the VCO is a selected multiple of the reference clock signal frequency.
FIG. 1 is a schematic of a typical PLL 100. The PLL 100 includes a phase comparator 110 having a first input for the reference clock signal and a second input for the feedback signal. Phase comparator 110 is shown to include simply an XOR logic gate for detection of the phase difference. The output of the phase comparator 110 is coupled to the input of a filter 120. The output of the filter 120 is coupled to the input of a VCO 130 for providing the control voltage to the VCO 130. The output of the VCO 130 is fed back to the second input of the phase comparator 110 through a frequency divider 140.
The filter 120 is shown to have a passive pre-filter 150 coupled in series with an active filter 160. The passive pre-filter 150 is generally an RC filter. The active filter 160 often includes an operational amplifier (op-amp) 170 configured as an integrator combined with a lead network (as shown). The active filter 160 could also be configured as an integrator combined with a lead/lag network by adding an additional capacitive component in parallel with the resistive component in the negative feedback loop. The pre-filter 150 is generally incorporated in PLLs of the type shown in FIG. 1 to avoid saturating the op-amp 170 of the active filter 160. The saturation potential results from the rectangular-wave output of the XOR phase detector of the phase comparator 110. However, as the frequency of the reference clock signal decreases, the amount of pre-filtering required generally increases. At low PLL bandwidths, pre-filtering of the reference clock becomes impractical, with the presence of the carrier (or clock) either causing the PLL to operate with unacceptable noise levels (known as Spurious Modulation) or, in the extreme case, not at all.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative systems capable of establishing a communications timing signal from a low-frequency reference clock signal.